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The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best
January-December 2005 (vol. 4 no. 1)
pp.
| ASCII Text | x | ||
| Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou, "The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best," IEEE Computer Architecture Letters, vol. 4, no. 1, pp. , January-December, 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2005.2, author = {Yiannakis Sazeides and Rakesh Kumar and Dean M. Tullsen and Theofanis Constantinou}, title = {The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best}, journal ={IEEE Computer Architecture Letters}, volume = {4}, number = {1}, issn = {1556-6056}, year = {2005}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2005.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best IS - 1 SN - 1556-6056 SP EP EPD - A1 - Yiannakis Sazeides, A1 - Rakesh Kumar, A1 - Dean M. Tullsen, A1 - Theofanis Constantinou, PY - 2005 VL - 4 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2005.2
This paper shows that if the execution of a program is divided into distinct intervals, it is possible for one processor or configuration to provide the best power efficiency over every interval, and yet have worse overall power efficiency over the entire execution than other configurations. This unintuitive behavior is a result of a seemingly intuitive use of power efficiency metrics, and can result in suboptimal design and execution decisions. This behavior may occur when using the energy-delay product and energy-delay product metrics but not with the energy metric.
Citation:
Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou, "The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best," IEEE Computer Architecture Letters, vol. 4, no. 1, Jan.-Dec. 2005, doi:10.1109/L-CA.2005.2
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