Issue No.01 - January-December (2004 vol.3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2004.3
Load misses in on-chip L2 caches often end up stalling modern superscalars. To address this problem, we propose hiding L2 misses with Checkpoint-Assisted VAlue prediction (CAVA). When a load misses in L2, a predicted value is returned to the processor. If the missing load reaches the head of the reorder buffer before the requested data is received from memory, the processor checkpoints, consumes the predicted value, and speculatively continues execution. When the requested data finally arrives, it is compared to the predicted value. If the prediction was correct, execution continues normally; otherwise, execution rolls back to the checkpoint. Compared to a baseline aggressive superscalar, CAVA speeds up execution by a geometric mean of 1.14 for SPECint and 1.34 for SPECfp applications. Additionally, CAVA is faster than an implementation of Runahead execution, and Runahead with value prediction.
Karin Strauss, James Tuck, Luis Ceze, Josep Torrellas, "CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction", IEEE Computer Architecture Letters, vol.3, no. 1, pp. 7, January-December 2004, doi:10.1109/L-CA.2004.3