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Thread-Sensitive Instruction Issue for SMT Processors
January-December 2004 (vol. 3 no. 1)
pp. 5
Simultaneous Multi Threading (SMT) is a processor design method in which concurrent hardware threads share processor resources like functional units and memory. The scheduling complexity and performance of an SMT processor depend on the topology used in the fetch and issue stages. In this paper, we propose a thread sensitive issue policy for a partitioned SMT processor which is based on a thread metric. We propose the number of ready-to-issue instructions of each thread as priority metric. To evaluate our method, we have developed a reconfigurable SMT-simulator on top of the SimpleScalar Toolset. We simulated our modeled processor under several workloads composed of SPEC benchmarks. Experimental results show around 30% improvement compared to the conventional OLDEST_FIRST mixed topology issue policy. Additionally, the hardware implementation of our architecture with this metric in issue stage is quite simple.
Citation:
Behnam Robatmili, Nasser Yazdani, Somayeh Sardashti, Mehrdad Nourani, "Thread-Sensitive Instruction Issue for SMT Processors," IEEE Computer Architecture Letters, vol. 3, no. 1, pp. 5, Jan.-Dec. 2004, doi:10.1109/L-CA.2004.9
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