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Issue No.01 - January-December (2004 vol.3)
pp: 1
ABSTRACT
Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional latency with pipelining, using "fat wires" at higher metal levels, and advances in process and material technology. We propose a stopgap solution to this problem by applying a decade old technique called bus-expanding to the problem. By exploiting low spatial and temporal entropy of data it is possible to transfer m bits of data over a n-bit wide bus in a single cycle (m > n ). High entropy data will be routed directly over the bus while low entropy data will be compacted using small lookup tables. A table index will be transferred in the case of a successful lookup, otherwise the full value will be transferred in several cycles. Reducing the number of wires per bus, enables the use of wider wires, which in turn reduces the wire delay. Examination of projected process technologies shows that by shrinking the number of bits in a bus (64 –> 48) instead of shrinking the individual wires maintains a constant wire delay. Tests on SPEC CPU2000 have shown that for the 64-bit buses leading from the L1 caches to the processor core it is possible to transfer all data types (addresses, integers, instructions and floating-points) using 40-bits per bus on the average.
CITATION
Daniel Citron, "Exploiting Low Entropy to Reduce Wire Delay", IEEE Computer Architecture Letters, vol.3, no. 1, pp. 1, January-December 2004, doi:10.1109/L-CA.2004.7
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