Issue No.01 - January-December (2004 vol.3)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2004.2
We apply recent results in queueing theory to propose a methodology for bounding the buffer depth and packet delay in high radix interconnection networks. While most work in interconnection networks has been focused on the throughput and average latency in such systems, few studies have been done providing statistical guarantees for buffer depth and packet delays. These parameters are key in the design and performance of a network. We present a methodology for calculating such bounds for a practical high radix network and through extensive simulations show its effectiveness for both bursty and non-bursty injection traffic. Our results suggest that modest speedups and buffer depths enable reliable networks without flow control to be constructed.
Arjun Singh, "Buffer and Delay Bounds in High Radix Interconnection Networks", IEEE Computer Architecture Letters, vol.3, no. 1, pp. 8, January-December 2004, doi:10.1109/L-CA.2004.2