Issue No.01 - January-December (2003 vol.2)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2003.4
Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures.
Out-of-order processor, memory latency, instruction-level parallelism, resource utilization, checkpointing.
Jos? F. Mart?nez, Josep Llosa, Mateo Valero, "A Case for Resource-conscious Out-of-order Processors", IEEE Computer Architecture Letters, vol.2, no. 1, pp. 7, January-December 2003, doi:10.1109/L-CA.2003.4