Issue No.01 - January-December (2003 vol.2)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2003.7
Trace-driven simulation has long been used in bothprocessor and memory studies. The large size of traces motivateddifferent techniques for trace reduction. These techniques oftencombine standard compression algorithms with trace-specificsolutions, taking into account the tradeoff between reduction inthe trace size and simulation slowdown due to decompression.This paper introduces SBC, a new algorithm for instruction anddata address trace compression based on instruction streams. Theproposed technique significantly reduces trace size andsimulation time, and it is orthogonal to general compressionalgorithms. When combined with gzip, SBC reduces the size ofSPEC CPU2000 traces 94-71968 times.
simulation, instruction and address trace, tracecompression
Aleksandar Milenkovic, Milena Milenkovic, "Stream-Based Trace Compression", IEEE Computer Architecture Letters, vol.2, no. 1, pp. 4, January-December 2003, doi:10.1109/L-CA.2003.7