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Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures
January-December 2003 (vol. 2 no. 1)
pp.
| ASCII Text | x | ||
| Rakesh Kumar, Keith Farkas, Norman P Jouppi, Partha Ranganathan, Dean M. Tullsen, "Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures," IEEE Computer Architecture Letters, vol. 2, no. 1, pp. , January-December, 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2003.6, author = {Rakesh Kumar and Keith Farkas and Norman P Jouppi and Partha Ranganathan and Dean M. Tullsen}, title = {Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures}, journal ={IEEE Computer Architecture Letters}, volume = {2}, number = {1}, issn = {1556-6056}, year = {2003}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2003.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures IS - 1 SN - 1556-6056 SP EP EPD - A1 - Rakesh Kumar, A1 - Keith Farkas, A1 - Norman P Jouppi, A1 - Partha Ranganathan, A1 - Dean M. Tullsen, PY - 2003 KW - chip multiprocessor KW - low-power architecture VL - 2 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2003.6
This paper proposes a single-ISA heterogeneousmulti-core architecture as a mechanism to reduce processorpower dissipation. It assumes a single chip containing a diverseset of cores that target different performance levels and consumedifferent levels of power. During an application?s execution,system software dynamically chooses the most appropriate core tomeet specific performance and power requirements. It describesan example architecture with five cores of varying performanceand complexity. Initial results demonstrate a five-fold reductionin energy at a cost of only 25% performance.
Index Terms:
chip multiprocessor, low-power architecture
Citation:
Rakesh Kumar, Keith Farkas, Norman P Jouppi, Partha Ranganathan, Dean M. Tullsen, "Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures," IEEE Computer Architecture Letters, vol. 2, no. 1, Jan.-Dec. 2003, doi:10.1109/L-CA.2003.6
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