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Implementing Decay Techniques using 4T Quasi-Static Memory Cells
January-December 2002 (vol. 1 no. 1)
pp. 10
This paper proposes the use of four-transistor (4T) cacheand branch predictor array cell designs to address increasingworries regarding leakage power dissipation. While 4T designslose state when infrequently accessed, they have very lowleakage, smaller area, and no capacitive loads to switch. Thisshort paper gives an overview of 4T implementation issues anda preliminary evaluation of leakage-energy savings that showsimprovements of 60-80%
Citation:
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark, "Implementing Decay Techniques using 4T Quasi-Static Memory Cells," IEEE Computer Architecture Letters, vol. 1, no. 1, pp. 10, Jan.-Dec. 2002, doi:10.1109/L-CA.2002.5
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